--
-- VHDL Architecture vga_lib.line_counter.arch
--
-- Created:
--          by - andax656.student (southfork-12.edu.isy.liu.se)
--          at - 10:22:29 10/05/11
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;

ENTITY line_counter IS
   PORT( 
      fpga_reset_n : IN     std_logic;
      vga_clk      : IN     std_logic;
      vga_hsync_n  : IN     std_logic;
      fpga_clk     : IN     std_logic;
      lcnt         : BUFFER integer RANGE 0 TO 525
   );

-- Declarations

END line_counter ;

-- Genererar lcnt
ARCHITECTURE arch OF line_counter IS
BEGIN
  process(fpga_clk)
    variable old_hsync_n : std_logic := '1';
  begin
    if rising_edge(fpga_clk) then
      
      if fpga_reset_n = '0' then
        lcnt <= 0;
        old_hsync_n := '1';
        
      elsif vga_clk = '1' then
        
        -- rising vga_hsync_n 
        if old_hsync_n = '1' and vga_hsync_n = '0' then
          if lcnt = 524 then
            lcnt <= 0;
          else
            lcnt <= lcnt + 1;   
          end if;       
        end if;
        old_hsync_n := vga_hsync_n;
        
      end if;        
    end if;
  end process;
END ARCHITECTURE arch;

